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Online Resumes with "Altera"
Principal FPGA Engineer and Senior Project Manager with a proven track record of consistently delivering high quality, world class products. Extensive experience delivering business solutions specializing in Xilinx and Altera FPGA for both the US and global companies. Strong track record of building high performance quality products, project management, collaboration and management of multiple teams internationally. Seeking...
My experience is selling mainly component level solutions into the Electronics industry to companies like IBM, EMC, Ciena, Coriant, Motorola. I am currently Regional Manager for Sumitomo Electric Device Innovations. My territory is the East Coast out to Chicago and Eastern Canada. I manage seven Manufacturer Rep Companies.
Proven, resourceful marketing manager driven to create compelling, honest, valuable online and print campaigns that generate high-quality sales leads for high-tech, Fortune 100 companies.
I am extremely passionate about pursuing a career in the semiconductor industry. I am a hardworking and a goal oriented person with a can do attitude.
I am only interested in contact work going forward. I want to be able to travel some a couple of months during the year. I will only work the North Houston area within 25 miles of The Woodlands or telecommute with limited travel if elsewhere. I would prefer embedded software work on microprocessors in C code. I have solid experience on TI ARM-4 and MSP430 processors. I also have recent QNX6.5 Neutrino with Photon APP Bui...
I am a Digital Electronics Design Engineer with a focus on digital design including FPGA design and simulation with a background in datacom and telecom. My experience includes design bring-up and circuitry troubleshooting of factory and field issues.
Tags for this Online Resume: Research Triangle Park, NC, Verilog, Cadence Concept, Viewlogic, Altera QuartusII, Factory Support, Field Support, PCB repair/modifications, Cellular, Crosstalk (Comm Sw), FPGA, Gateway, Layout, Manufacturing, T1, GE, Cellular, Crosstalk (Comm Sw), FPGA, Gateway, Layout, Manufacturing, T1, GE
ELECTRONICS AND ELECTRICAL DESIGN, ANALYSIS
and Compared testability to ATPG. Gate sizing to optimize area and overall maximum delay using C++ November 2015 * Implemented Lagrange relaxation for circuit to optimize overall area subjected to delay less than maximum delay. * Developed C++ source code using classes to implement both algorithm and successfully achieve excellent result.* Designed 8 --bit Microprocessor ASIC with AMI 0.6um
CAREER POSITION IN ELECTRICAL ENGINEERING
Master's graduate of Southern Methodist University's Electrical engineering program seeking a position as a Circuit Design Engineer. Offering technical expertise in Analog, Digital and Mixed signal circuit design, layout and verification.
Colorado Space Grant Consortium SIMBA team: 2014 - 2015 * Design Printed Circuit Board to control humidity sensor pressure sensor and provide power for the payload to collect information on Earth's stratospheric microorganisms. * Connect Raspberry Pi to control the sensors