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Online Resumes with "LVS"
Tags for this Online Resume: ASIC Digital Logic Design using Verilog (RTL), Functional Verification using System Verilog (HVL), Layout of 4-stage router pipeline using DRC,LVS, Computer Architecture with pipelining using C++, Linux operating system, Synopsys design vision
Micro-Electronics Engineering. IC Digital&Analog CMOS,BCMOS mix-signal Design. DRC and LVS,ERC Chip planning Block cell level and Standar Libaries cell. Used Mentor Garphic or Cadence CAD Tools to make chip plan.
A mixed signal IC designer with ten years experience in the field of consumer / medical / scientific / industrial imaging devices(mainly CMOS and CCD). Experienced at block level and system level imager design from conception through silicon. Ability to work well as both an individual contributor or group member. Adept at working in cross functional teams to come up with working solutions for difficult problems.
IC Mask Layout Designer - 3 years Working with Caliber to floor plan from scratch with area estimates, integrate sub-block signal flow, preliminary device placements, run my own layout design reviews using the projector with Virtuoso XL, complex wiring st
I am a well-qualified mask layout designer with over 2 years of working experience with a fantastic team of highly experienced designers at the Colorado-RFMD design center. It is through Layout Design that I have found my passion for problem solving. I feel I have found my calling with Mask Layout design and look forward to my future in this profession. My fresh prospective and motivation bring new ideas to complex layout....
I have experience in Analog, Bipolar and CMOS Digital design. I am fluent with Cadence VXL, Calibre LVS, Calibre DRC and Hercules DRC and LVS. Experienced with the Pulsic Router for digital standard cell routing.
Looking for IC Layout Designer position.
SUMMARY I've been working in layout / auto P&R field for almost 18 years and with strong background on the back-end side. I've also been working on timing driven P&R for the last 10 years.
Perform the following tasks such as writing Design and Development RTL coding/fixing Simulation Sythesis Lint checking Clock Domain Crossing (CDC) Analysis Scan insertion for DFT Formal Verification Floorplanning Power Planning Place & Route LVS/DRC/Antenna clean final sign-off using for Static Timing Analysis (STA) Power Analysis Integration for Cluster level & Toplevel and also resolving SI issues for the following compan...
SUMMARY Senior physical design engineer with 18 years' experience in various layout styles including custom, cell-based and RLS, with particular expertise in memory compiler design. Extensive experience with 14nm and 10nm processes technologies. Skillful in layout planning, implement, verification and debugging. Experience in: * Layout design CAD tools: GeneSys, Opus, Virtuoso, Hercules, ISS, RV, SURF * Physical verificatio...
SUMMARY •US permanent resident fully authorized to work in the US (Green Card, EB-11) •PhD in Electronic Engineering from The University of Tokyo in Japan and Xi’an Jiaotong University •10 years hardware and chips experience including the development of video and image processing/monitoring chips, Closed loop trajectory correction system chips based on real time graph and image feedback, Video codec development based on H....
EXPERIENCE SUMMARY: Proficient C/C++ software development STL, Multi-threading, Tcl, Perl, Linux/Unix/Windows EDA/CAD, Global & Detail & ECO routing, VLSI/ASIC designs DRC/LVS physical layout verification