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Online Resumes with "Physical Design Engineer"
Ideal Companies: Any company
I have six years of experience in Physical Design. I am currently working on the technology scale down project at ARM as contractor. I have exposure to the prominent tools from Synopsys, Mentor Graphics and Cadence like IC Compiler, Astro, AstroRail, StarRC-XT, PrimeTime,PrimeRail, Calibre, SOC Encounter and Nano Router.
Responsible for Physical Design Engineering like Floor planning, Static timing Analysis, Placement and Routing, Layout Design.
5 years of experience in Physical Design. I have exposure to the prominent tools from Synopsys, Mentor Graphics and Cadence like IC Compiler, Astro, AstroRail, StarRC-XT, PrimeTime,PrimeRail, Calibre, SOC Encounter and Nano Router.
Seeking a challenging and enduring job in professional organization where my skills & abilities could be fully utilized to achieve organizational goals and professional growth.
Seeking a challenging position in a team environment that will utilize and maximize my skill as an Electrical Engineer for mutual benefits.
Work on the challenging issues of UDSM (Ultra Deep Sub Micron) Physical Design in SoC environment.
To look for position of physical design engineer in growing company
I’m an experienced Physical Design engineer, including architecture, design, verification and integration. Experienced in custom cells creation, structure modules building; including floor planning, IO macros creating and integration, power grid building for blocks/chip level. Excellent performance in problem solving and debugging. Fast learning of new environments.
ASIC PHYSICAL DESIGN ENGINEER Dedicated team player and tenacious problem solver with 15 years of experience. Extensive Hardware, Software, ASIC and VLSI Design background in Synthesis, Static Timing Analysis, Formal Verification, Place&Route, and SoC IP integration. Extensive experience in scripting with PERL, C, TCL, CSH, and Synopsys Tools.
Ideal Companies: no interviews no offers
Seeking an IC/CAD/SoC physical design engineering position QUALIFICATION * 16-year experiences in high-speed, low-power, billion-transistor, deep sub-micron CPU design * 3-yearexperience in sophisticated SoC design * Taped out 7 Intel CPU chips and 2 Broadcom communication chips
Tags for this Online Resume: Intel Co., Noise, Perl Programming Language, Sub-micron, Automation, Layout, Reliability, CAD flow, EDA tools, System engineering, synthesis, IRdrop/EM/ESD, STA, PnR, RC Extraction, CTS, Low power
Summary An Advanced IPC Certified PWB Physical Design Engineer (IPC CID+) with 20 years of demonstrated producible PWB design experience. PWB Design from footprint creation to board vendor builds capable in all aspects of PWB Design including Librarian experience. Desires a Physical PWB Design, Quality, Packaging or Producibility Engineer position. Poses strong self-discipline, strong work ethic and positive professional at...